1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and, more particularly, to semiconductor integrated circuit devices that include a high voltage generator.
2. Description of Related Art
Semiconductor memories are vital components of a wide array of electronic devices. Semiconductor memory devices can be characterized as volatile memory devices and non-volatile memory devices.
In volatile memory devices, logic information is stored either by setting the logic state of a bistable flip-flop such as is done in a static random access memory (SRAM), or through the charging of a capacitor as is done in a dynamic random access memory (DRAM). In either case, the data is stored and can be read out only while power is applied. The stored data is lost when power is turned off.
Non-volatile memory devices, such as MROM, PROM, EPROM, and EEPROM devices, are capable of storing the data even with power turned off. The non-volatile memory data storage mode may be permanent or reprogrammable depending on the technology used. Non-volatile memories are often used for program and microcode storage in a wide variety of devices.
A combination of single-chip volatile as well as non-volatile memory storage devices is also available in devices such as non-volatile SRAM (nvSRAM) devices. Such devices are generally used in systems that require fast and reprogrammable non-volatile memory. In addition, many special memory architectures have evolved which contain additional logic circuitry to optimize performance for application-specific tasks.
With non volatile semiconductor memory devices, since MROM, PROM, and EPROM devices, it is difficult for users to renew the memory content. To the contrary, EEPROM devices are electrically erasable and readable, thus it is easy to renew the memory content of such devices. Such devices are often used to store system programming that requires continuous renewal. Flash EPROM (hereinafter referred to as “flash memory”) devices are suitable for large capacitance subsidiary memory devices because flash memory has higher integration than conventional EEPROM devices. NAND-type flash memories have even higher integration than NOR-type flash memories.
In flash memories, if memory cells are programmed once, the programmed memory cell must be erased in order to store new data. That is, flash memories do not support an overwrite function. Methods for programming and erasing general flash memories are, for example, disclosed in U.S. Pat. No. 6,061,270 entitled “METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL”, U.S. Pat. No. 6,335,881 entitled “METHOD FOR PROGRAMMING A FLASH MEMORY DEVICE”, and U.S. Pat. No. 6,370,062 entitled “NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME”.
In general, in order to erase or program a memory cell in a non-volatile memory device, higher voltage than the power supply voltage is required. An example of circuitry to generate such a high voltage is disclosed in U.S. Pat. No. 5,642,309 entitled “AUTO-PROGRAM CIRCUIT IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE”.
FIG. 1 herein shows a circuit diagram of conventional high voltage generator circuit such as that shown in U.S. Pat. No. 5,642,309. With the circuit shown in FIG. 1, a program voltage Vpgm generated from a high voltage generator 10 is divided by trimming circuit 30. The divided voltage is compared with a reference voltage Vpref by a comparator circuit 40. A control circuit 20 controls the transmission of clock signals to the high voltage generator 10 based on the output of the comparator. The control circuit 20 generates clock signals ΦPP and /ΦPP which provide inputs to the high voltage generator 10. The high voltage generator 10 is a charge pump. The generator 10 is turned on and off according to the result of the comparison between the divided voltage and the reference voltage.
The clock signals ΦPP and ΦPP are generated from the time voltage Vpgm reaches a target level Vtarget, to the time that the charge pump is turned off. This may generate additional or unnecessary clock signals. Due to the additional or unnecessary clock signals ΦPP and /ΦPP, the voltage Vpgm rises to be higher than the target level Vtarget, as illustrated in FIG. 2. As a result, the voltage Vpgm is irregularly maintained, that is, a ripple phenomenon occurs.